As FPGA designs increase in complexity, directed verfication and burn and churn approaches soon cause a debug nightmare. Deploying a constrained random, metrics driven and coverage closed verification approaches from the onset reduces the surprises in the lab bring up greatly reducing the debug time and verification effort. We help you transition to newer methodolgies and also preserving your investment in legacy environments and tools.
A well written testbench helps you improve your design quality and reduce your respin costs. Reuse of verfication efforts reduces your overall verification time. Our verfication consultants create reusable and scalable verification environments for your products. We have extensive experience in UVM, SV or UVM-e. We can do staff augmentation to partial or total outsourced development.
In cooperation with our strategic partners we offer full turn-key FPGA development and verification, ASIC/SOC verification.
We offer industry leading instructions on UVM, SV, UVM-e with onsite and offsite courses. Our labs are based on examples from the industry that can bring your development and managment teams up to speed on techniques leveraged in verifcation. We can also custom prepare the courses to have scenarios closer to your application domains.
Migrating a directed testbench to methodology based, resuable, coverage driven, constrained random testbench is a complicated process and requires expert knowledge. We have experience with several clients and help you achieve this successfully and safely.
Verification planning, metrics gathering and subsequent tracking for coverage closure is an important aspect of verifcation that determines the quality of the verification process. In this important aspect we proivide consultancy to coordiante your planning effort and associate the implementations with a live test-plan to ease the tracking effort
In cooperation with our strategic partners we offer formal verification services to augment your existing environments. We can also train your teams on assertion based verfication and develop features to bind, track and measure these in your environments.
WIRSYS has created testbenches for PHY layers of 802.11ac, 802.11ax, 802.11ad modems. We are an elite team of verfication experts that have been awarded key patents in forward error correction - LDPC, Turbo decoding, Viterbi decoding etc and have also published extensively in these and other wireless signal processing areas. We have worked in virtualizion domains using PCIe and NVMe transport on large FPGAs and also on several networking products. Our consultants are skilled across the full range of the most powerful modern tools, technologies and methods.
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